1. Field of the Invention
The present invention relates to a noise reduction apparatus and method.
2. Description of the Related Art
Since power consumption is generally proportional to a square of applied power voltage, dropping the power voltage may be an effective method of reducing the power consumption. Accordingly, a dynamic voltage scaling (DVS) technique has been developed to dynamically reduce power voltage of a CPU in a computer system.
In the meantime, power management of an operating system is performed based on, for example, the Advanced Configuration and Power Interface (ACPI) power management specification in recent mobile PC environments.
According to the power management specification, operation modes of a CPU are defined as C0, C1, C2, C3, C4, C5, and C6 states in order to efficiently utilize power that is used in a system. Here, the C0 state is a normal state, and the C2 state is a step in which the CPU performs a minimum activity such as snooping operation in order to maintain associativity of cache. The C3 state is a state in which an external clock is not provided to the CPU, and all activities except a function for maintaining data stored in a cache memory within the CPU are suspended. In addition, the C4 and C6 states are power states that minimize power consumption by lowering voltage supplied to the CPU.